1. Field
Exemplary embodiments of the present disclosure relate to transistors and methods of fabricating the same and, more particularly, to vertical gallium nitride transistors and methods of fabricating the same.
2. Discussion of the Background
In the electronics industry, high voltage transistors operating at a high speed are increasingly in demand with the development of information and communication techniques. In response to such a demand, use of gallium nitride (GaN) transistors has been proposed. GaN transistors may exhibit a relatively fast switching characteristic and a relatively high breakdown voltage characteristic as compared with conventional silicon transistors. Thus, GaN transistors may be very attractive as candidates for improving the performance of communication systems. Particularly, high electron mobility transistors (HEMTs) fabricated using a gallium nitride (GaN) material may operate using a two-dimension electron gas (2DEG) generated at an interface in a heterogeneous material. Thus, electron mobility of the HEMTs may be improved to allow the HEMTs to operate at a high speed.
In general, GaN transistors may be fabricated to have a planar-type configuration. In such a case, there may be a limitation in improving carrier mobility. This is because an electric field at a channel surface disturbs movement of the carriers. Further, when the planar-type GaN transistors operate, an electric field may be concentrated at corners of gate electrodes of the planar-type GaN transistors. This may lead to degradation of the breakdown voltage characteristic of the planar-type GaN transistors.
Recently, vertical GaN transistors have been proposed to solve the above disadvantages. For example, current aperture vertical electron transistors (CAVETs) are taught in U.S. patent publication No. US 2012/0319127 A1 to Chowdhury et al., entitled “current aperture vertical electron transistors with ammonia molecular beam epitaxy grown P-type gallium nitride as a current blocking layer”. According to the U.S. patent publication No. US 2012/0319127 A1, a source electrode and a drain electrode are disposed to vertically face each other, and a P-type gallium nitride (P-GaN) layer acting as a current blocking layer is disposed between the source and drain electrodes. Accordingly, a channel current may flow in a vertical direction from the drain electrode toward the source electrode, through an aperture provided by the P-type gallium nitride (P-GaN) layer.
In order to fabricate the vertical GaN transistors, a process for epitaxial growth of a GaN layer may be used. For example, the GaN layer may be grown on a c-plane sapphire substrate using a metal organic chemical vapor deposition (MOCVD) process for reasons of low fabrication cost in spite of a relatively high lattice constant and a thermal coefficient mismatch. However, the GaN layer grown on the c-plane sapphire substrate using the MOCVD process may have a high defect density because of a lattice constant difference between the c-plane sapphire substrate and the GaN layer grown on the c-plane sapphire substrate. That is, a number of threading dislocations (TDs) may be formed in the GaN layer to be parallel with a growing direction of the GaN layer. The threading dislocations (TDs) may act as non-radiative recombination centers or charged scattering centers to affect the mobility of the carriers. In particular, if the threading dislocations (TDs) are formed to be parallel with a vertical direction corresponding to a movement direction of the carriers in the vertical GaN transistors, a breakdown voltage of drain junctions of the vertical GaN transistors may be remarkably reduced, and may degrade the reliability of the vertical GaN transistors.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form any part of the prior art nor what the prior art may suggest to a person of ordinary skill in the art.